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| YDA148 catalog catalog no.:lsi-4da148a31 2007.9 YDA148 d-510 stereo 5w-15w digital audio power amplifier overview YDA148 (d-510) is a high-efficiency digital audio power amplifier ic with the maximum output of 15w 2ch. YDA148 has a ?pure pulse dir ect speaker drive circuit? th at directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate characteristics and low noise char acteristics among digital amplifier ics in the same class. in addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use conditions. YDA148 features power limit function, non-clip function, and drc (dynamic range control) function that were developed by yamaha original digital amplifier technology. YDA148 has overcurrent protection function for speaker output terminals, high temperature protection function, and lowsupply voltage malfunction prevention function. features ~ operating supply voltage range pvdd: 8.0v to 16.5v ~ maximum momentary output 15 w2ch (v ddp =15v, r l =8 ? , thd+n=10%) ~ maximum continuous output 15 w* 1 2ch (v ddp =15v, r l =8 ? , thd+n=10%, ta=70c) ~ distortion rate (thd+n) 0.01 % (v ddp =12v, r l =8 ? , po=0.1w, 1khz) ~ residual noise 48vrms (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ~ efficiency 91 % (v ddp =12v, r l =8 ? ) ~ s/n ratio 105 db (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ~ channel separation -80 db (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ~ psrr 60db (v ddp =12v,vripple=100mv, 1khz, gain[1:0]=l,l, ncdrc[1:0]=l,l) ~ non-clip function/drc function (switchable) ~ power limit function ~ clock external synchronization function ~ master/slave synchronization function using clock outputs ~ over-current protection function, high temperature protection function, low voltage malfunction prevention function, and dc detection function ~ sleep function using sleepn terminal and ou tput mute function using muten terminal ~ stereo/monaural switching function ~ spread clock function ~ pop noise reduction function ~ package lead-free 32-pin plastic qfn (exposed stage) note) *1: a value based on yamaha's board implementation conditions (see note *2 of page 25) free datasheet http://
YDA148 2 terminal configuration < 32-pin qfn top view > free datasheet http:// YDA148 3 terminal function no. name *4) i/o *1), *2), *3) function 1 pvddreg pvdd power supply terminal for regulators 2 avdd oa 3.3v regulator output terminal 3 inlp ia analog input terminal (lch+) 4 inlm ia analog input terminal (lch-) 5 vref oa reference voltage output terminal 6 inrm ia analog input terminal (rch-) 7 inrp ia analog input terminal (rch+) 8 avss gnd analog ground terminal 9 plimit ia power limit setting terminal 10 pvddpr pvdd power supply terminal fo r digital amplifier output (rch+) 11 outpr o digital amplifier output terminal (rch+) 12 outpr o digital amplifier output terminal (rch+) 13 pvssr gnd ground terminal for digital amplifier output (rch) 14 outmr o digital amplifier output terminal (rch-) 15 outmr o digital amplifier output terminal (rch-) 16 pvddmr pvdd power supply terminal fo r digital amplifier output (rch-) 17 sleepn i sleep control terminal 18 protn o/d error flag output terminal 19 muten i mute control terminal 20 ckout o clock output terminal for synchronization 21 ckin i external clock input terminal 22 ncdrc0 i non-clip/drc1/drc2 mode selection terminal 0 23 ncdrc1 i non-clip/drc1/drc2 mode selection terminal 1 24 gain0 i gain setting terminal 0 25 gain1 i gain setting terminal 1 26 pvddml pvdd power supply terminal for digital amplifier output (lch-) 27 outml o digital amplifier output terminal (lch-) 28 outml o digital amplifier output terminal (lch-) 29 pvssl gnd ground terminal for digital amplifier output (lch) 30 outpl o digital amplifier output terminal (lch+) 31 outpl o digital amplifier output terminal (lch+) 32 pvddpl pvdd power supply terminal fo r digital amplifier output (lch+) (note) *1 i: input terminal, o: output terminal, a: analog terminal, o/d: open/drain output terminal *2 pvdd should be connected each other on a board. *3 gnd should be connected each other on a board. *4 each output terminal with the same name (outpr , outmr, outpl, and outml) should be connected on a board. free datasheet http:// YDA148 4 block diagram free datasheet http:// YDA148 5 functional description ? digital amplifier function YDA148 has digital amplifiers with analog input, pwm pulse output, the maximum output of 15w 2ch. adopting ?pure pulse direct speaker drive circuit? reduces distortion and noise on pwm pulse output signal. ~ digital amplifier gain the total gain of the digital amplifier varies depending on operation modes, as shown below. ncdrc1 ncdrc0 gain1 gain0 total gain operation mode l l +22db l h +28db h l +34db l l h h +16db normal mode non-clip: off drc: off l l +34db l h +40db h l +46db l h h h +28db non-clip mode l l +34db l h +40db h l +46db h l h h +28db drc1 mode l l +34db l h +40db h l +46db h h h h +28db drc2 mode ~ audio signal input for a differential input, the signal should be input to inlp and inlm terminals (lch) and to inrp and inrm terminals (rch) through a dc-cut capacitor (c in ). on the contrary, for a single-ended input, the signal should be input to inlp terminal (lch) and to inrp terminal (rch) through a dc-cut capacitor (c in ). at this time, inlm and inrm terminals s hould be connected to avss through dc-cut capacitors (c in ) with the same value. in the differential input mode, use signal sources with the same impedance to reduce pop-noise. its value should be 10k ? or less. use a dc-cut capacitor (c in ) of 1f. (the capacitance value should be less than 1.5f throughout the operating temperature range.) (cautions) when inputting audio signals in power-off state ( pvdd < v huvll ) or sleep state, current may flow toward the former device from YDA148's ground, through each protection circuit of analog pins (inlp, inlm, inrp, and inrm). for this reason, audio signals should not be input in power-off state ( pvdd < v huvll ) or sleep state. free datasheet http:// YDA148 6 " 7 % % 1 - * . * 5 " 7 4 4 7 p m u b h f % j w j e j o h 3 f t j t u p s 3 7 p m u b h f % j w j e j o h 3 f t j t u p s 3 plimit terminal setting circuit ~ input impedance the input impedance (z in ) is 18.8k ? regardless of a gain setting. ~ reference voltage output function half a voltage of avdd terminal is output to the reference voltage terminal (vref). connect a capacitor of 0.1 f for voltage stabilization. ~ maximum output the output varies depending on load impedance and a supply voltage, as shown below. maximum momentary output 15w 2ch (pvdd=15v, r l =8 ? , thd+n=10%) maximum continuous output 15w 2ch (pvdd=15v, r l =8 ? , thd+n=10%, ta=70 ? ) the maximum momentary output means a possible maximum output by considering heat problems due to power loss separately. the maximum continuous output means a maximum ou tput with tjmax not ex ceeding 150c at a given temperature while outputting a sine wave continuously. in addition, this value is based on yamaha's board implementation conditions. (see note *2 of page 25) a possible maximum continuous output in other settings can be converted by the following data: 1. graph of power dissipation vs output power of example of typical characteristics. (see page 29) 2. power dissipation of electrical characteristics. (see page 25) ? control function ~ output power limit function this is the function to set a voltage at which the output is clipped. at this time, a value at which the output is clipped is defined as a power limit value (v pl ). using this function prevents increase of temperature in a device as well as allowing the maximum output power to be limited. the output power limit value is determined by a voltage (voltage dividing resistor 1, 2) applied to plimit terminal. in addition, changing the voltage at plimit terminal during power-on is prohibited. the relation between a resistor ratio ( 3 3 3 between voltage dividing resistor 1 and 2) and an output power with a 10% distortion is shown below. since it may vary between min and max due to variation of internal avdd, select resistors in consideration of the variation. the setting values shown here are common to stereo and monaural mode. plimit resistor r1 and r2 should be set as follows. r1+r2=500k ? or less r1//r2=50k ? to 70k ? (r1//r2 means a parallel resistance between r1 and r2) example 1: 4 ? max30w (8 ? max15w) r1=220k+4.7k, z r2=75k example 2: 8 ? min10w r1=200k, r2=75k+1.5k free datasheet http:// YDA148 7 . j o j n v n w b m v f s f t u s j d u j p o p o u i f p v u q v u q p x f s m j n j u 5 i f n j o j n v n w b m v f p g u i f p v u q v u q p x f s m j n j u w b m v f t j t s f t u s j d u f e c z u i f w b m v f e f u f s n j o f e x j u i u i f s f t j t u b o d f w p m u b h f e j w j t j p o s b u j p p g l z & w f o u i p v h i u i f s f t j t u b o d f w p m u b h f e j w j t j p o s b u j p j t t f u c f z p o e l z u i f p v u q v u q p x f s m j n j u w b m v f x p v m e o ` u c f t f u m p x f s $ b o d f m m b u j p o p g u i f p v u q v u q p x f s m j n j u g v o d u j p o * u j t q p t t j c m f u p e j t b c m f u i f q p x f s m j n j u c z t f u u j o h l z 7 w p m u b h f e j w j t j p o s b u j p l z u p u i f 1 - * . * 5 q j o enlarged figures 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p w t 0 v u q v u 1 p x f s b u ? e j t u p s u j p o 1 - * . * 5 7 p m u b h f % j w j e j o h 3 b u j p 0 v u q v u 1 p x f s b u ? e j t u p s u j p o < 8 > 5 z q . * / . " 9 free datasheet http:// YDA148 8 ~ non-clip/drc function this is the function to change the gain by detecting an inpu t level to the pwm amplifier and to raise an average output level while suppressing clipping. a mode is determined by the combination of ncdrc[1:0] terminals, as shown below. ncdrc1 ncdrc0 mode l l non-clip & drc mode off l h non-clip mode h l drc1 mode h h drc2 mode in non-clip mode, the gain increases by 12db. the gain is automatically adjusted so that an output peak voltage becomes a power limit value. the maximum attenuation is -12db. attack time is 0 second. the release time from -12db to 0db is 7.7 s (typ.). in drc1 mode, the gain increases by 12db. dynamic range compression (a half of gain in db) is performed within an output range of -12db (-24db for input range) from the power limit value. attack time is 0 s. the release time from -12db to 0db is 3.9 s (typ.). in drc2 mode, the gain increases by 12db. as with drc1, similar compression is performed, but power-limit operation is not performed. plimit terminal can be used to set a d rc operating point. therefore, the setting of a gain curve is possible regardless of the maximum output power, and this allows for drc operation from a low output power. ncdrc [1:0] terminal should be switched under either of the following conditions. ~ before pvdd power-on (lower than the pvdd start-up threshold voltage (v huvlh )) ~ sleepn=l pop noise may occur when switching it under an operating condition other than the above. free datasheet http:// YDA148 9 0 v u q v u 7 p m u b h f < e # > * o q v u 7 p m u b h f < e # > 0 ' ' / $ % 3 $ < > 1 p x f s - j n j u 7 b m v f 7 1 - " d p o e j u j p o j o x i j d i u i f q p x f s m j n j u j t c f j o h b q q m j f e non-clip/drc gain curve (off) 0 v u q v u 7 p m u b h f < e # > * o q v u 7 p m u b h f < e # > 0 ' ' / $ % 3 $ < > 1 p x f s - j n j u 7 b m v f 7 1 - " d p o e j u j p o j o x i j d i u i f q p x f s m j n j u j t c f j o h b q q m j f e / p o d m j q / $ % 3 $ < > non-clip/drc gain curve (non-clip) output voltage [db] output voltage [db] free datasheet http:// YDA148 10 z? ?y < e # > ?? ?y < e # > 0 ' ' / $ % 3 $ < > ?????? ? 7 1 - ??????u? tlom? y 6 % 3 $ / $ % 3 $ < > 7 1 - e # non-clip/drc gain curve (drc1 0 v u q v u 7 p m u b h f < e # > * o q v u 7 p m u b h f < e # > 0 ' ' / $ % 3 $ < > 1 p x f s - j n j u 7 b m v f 7 1 - " d p o e j u j p o j o x i j d i j u j t o p u b q q m j f e f w f o j g f y d f f e j o h u i f q p x f s m j n j u % 3 $ / $ % 3 $ < > 7 1 - e # non-clip/drc gain curve (drc2 power limit value ( v pl ) a condition in which the power limit is being applied. output voltage [db] input voltage [db] output voltage [db] free datasheet http:// YDA148 11 ~ sleep function YDA148 shifts into sleep mode when sleepn terminal goes to ?l? level. in the sleep mode, all functions stop and consumption current is minimized ( sleep ). when shifting into sleep mode during any protection mode, the protection mode is cancelled and protn terminal output becomes hi-z state. the digital amplifier output becomes weak low (a state grounded through a high resistance). avdd and vref outputs are pulled down. when the level at sleepn terminal is changed from ?l? to ?h? under the condition th at the voltage at pvddreg terminal is higher than the threshold voltage (v huvlh ) for low voltage malfunction prevention cancellation, the sleep mode is cancelled and the state shifts into the normal ope ration state after the period of sleep recovery time (t wu ). ~ mute function YDA148 shifts into mute mode when muten terminal goes to ?l? level. in the mute mode, the digital amplifier output becomes weak low (a state grounded through a high resistance). when the level at muten terminal is changed from ?l? to ?h? under the condition that the voltage at pvddreg terminal is higher than the threshold voltage (v huvlh ) for low voltage malfunction prevention cancellation and state of sleepn terminal=h, the mute mode is cancelled and the state shifts into the normal operatio n state after the period of mute recovery time (t mrcv ). ~ clock control function the setting of ckin terminal controls the clock mode as shown below. ckin terminal setting mode ckout l fixed internal clock mode internal clock (frequency: f ck ) output h fixed internal clock (spread clock) mode internal clock (spread clock) frequency: (f ck ) output clock input external clock mode ckin input buffer output (frequency: f ckin ) when ckin terminal is held l or h level, internal clock mode is selected to generate a clock internally. and, when ckin terminal is held h level, spread clock function operates to reduce emi. when an external clock is input to ckin terminal, its frequency should be f ckin . do not use with ckin terminal left open. ~ stereo/monaural switching function when inrp and inrm terminals (rch input) are connected to avdd, monaural mode is selected. in the monaural mode, input signals input to inlp and inlm terminals (lch input) are output from lch and rch digital amplifiers. with the monaural mode, parallel operation can be realized by connecting outpl to outpr and connecting outml to outmr. for details of connections, see ?single operation in monaur al mode? (see page 20) in the ?examples of application circuits.? the switching between stereo and monaural modes should be performed under the following conditions. ~ before pvdd power-on (lower than the pvdd shut-down threshold voltage) ~ digital amplifier pop noise reduction function pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by minimizing an output offset voltage. ~ multi-chip synchronization function the external clock synchronization function and clock output function are prepared and the use of master/slave configuration realizes carrier clock synchronization. when using it with multi chips synchronized, one is used as a ma ster chip and the other is used as a slave chip. at this time, connect ckout terminal of a master ch ip to ckin terminal of a slave chip. when using 3 chips (master/slave1/slave2), connect ckout terminal of a slave1 chip to ckin terminal of a slave2 chip. for details of connections, see ?master-slave operation? (see page 23 and 24) in the ?examples of application circuits.? pvdd pins should be connec ted each other on a board. free datasheet http:// YDA148 12 ~ startup sequence, shutdown sequence 7 ) 6 7 - ) 1 7 % % 0 6 5 1 - 0 6 5 1 3 7 % % 1 u 8 6 0 6 5 . - 0 6 5 . 3 % j h j u b m " n q m j g j f s 0 v u q v u " 7 % % 7 % % " power supply startup sequence 7 ) 6 7 - ) 1 7 % % 0 6 5 1 - 0 6 5 1 3 7 % % 1 0 6 5 . - 0 6 5 . 3 % j h j u b m " n q m j g j f s 0 v u q v u 4 u p q q j o h % j h j u b m " n q m j g j f s 0 v u q v u " 7 % % 7 % % " power supply shutdown sequence free datasheet http:// YDA148 13 7 * ) @ 4 - 1 / 4 - & & 1 / 0 6 5 1 - 0 6 5 1 3 u 8 6 0 6 5 . - 0 6 5 . 3 % j h j u b m " n q m j g j f s 0 v u q v u " 7 % % startup sequence from sleep state 7 * - @ 4 - 1 / 4 - & & 1 / 0 6 5 1 - 0 6 5 1 3 0 6 5 . - 0 6 5 . 3 % j h j u b m " n q m j g j f s 0 v u q v u 4 u p q q j o h % j h j u b m " n q m j g j f s 0 v u q v u " 7 % % transient sequence to sleep state free datasheet http:// YDA148 14 ? regulator output when sleepn terminal is at h, YDA148 outputs v dda to avdd terminal. connect a capacitor of 1f to 4.7f to avdd terminal for stabilization. (0.8f or more should be secured including its varia tion and temperature change.) avdd output must be used only for YDA148. if this output is used in a peripheral circuit of YDA148, the maximum current that can be driven will be i dda. ? lc filter YDA148 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance the speaker has, and this allows for direct c onnection to a speaker without an lc filter. when an lc filter is used, use the lc filter circuits shown below. at this time, the following constant should be used according to an impedance of a speaker. using these constants makes a low-pass filter with a cu t-off frequency of 50khz or so, q=0.7 or so. lc filter constants: 3 - - $ $ ) ' ' ) ' ' $ $ $ 3 - - - $ $ $ 3 - - - - $ ' j m u f s d j s d v j u 4 u f s f p - $ ' j m u f s d j s d v j u . p o b v s b m with use of lc filters, if there is a possibility of not usin g a speaker, audio signals within 20khz should be input. and, if its band limitation is not possible, remove the speaker under the following conditions: sleepn terminal = l or muten terminal = l, or pvdd = power off. ? speaker inductance in the following cases, use a speaker w ith an inductance of 20h or more (at around the switching frequency (f ckin or f ck )). 1. direct connection of a speaker to an output pi n of the digital amplifier without an lc filter. 2. connection of a speaker to a position after components fo r emi measures such as ferrite beads etc. (filterless). with an inductance of less than 20h, power lo ss in the speaker and this device may increase. free datasheet http:// YDA148 15 ? protection function YDA148 has the following four digital amplifier protection functions: overcurrent protection function, high temperature protection function, low voltage malfunction prevention function, and dc detection function. protection functions protn terminal output protn terminal latch digital amplifier output state protection mode cancel over current protection function low latched wl *1) sleepn terminal=l or pvdd shutdown high temperature protection function (high temp. power limiter state) not latched power limit (-6db) sleepn terminal=l or pvdd shutdown or lower temperature high temperature protection function (high temp. shutdown state) low not latched wl *1) sleepn terminal=l or pvdd shutdown or lower temperature low voltage malfunction prevention function (highz) wl *1) dc detection function low latched wl *1) sleepn terminal=l or pvdd shutdown *1: wl=weak low (a state when gr ounded with a high resistance) use a circuit as shown below when pulling up protn terminal output externally. 1) pull up the terminal to a voltage obtained by dividing the voltage between pvdd and gnd with voltage-dividing resistors. find values with reference to the following formula so th at a voltage at the terminal becomes 3.3v or less when protn terminal is in ?h? output (hi-z). 2.0v ? (r2 / (r1 + r2)) v ddp ? 3.3v ;however, r1 > 100k ? , 10k ? < r2 < 100k ? 2) the pull-up should be performed to an external supply vo ltage lower than 3.3v. the pull-up resistor r3 should be a value as follows. 40k ? < r3 < 200k ? (47k ? is recommended.) in each case, select these values so that 0.4ma or more curren t will not flow into the terminal while protn terminal is in l state. protn terminal pull-up connection 1 (a pull-up to pvdd) free datasheet http:// YDA148 16 7 $ $ 7 1 3 0 5 / 3 & s s p s ' m b h protn terminal pull-up connection 2 (a pull-up to 3.3v) * if automatic return setting is given by connecting protn terminal to sleepn terminal, use a separate power supply as vcc, not the same power supply as avdd. * when vcc is used as avdd, see st artup sequence (page 12 and 13). free datasheet http:// YDA148 17 ~ digital amplifier over current protection function this is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between terminals) at digital amplifier output terminals. in the protection mode, protn terminal becomes l level and output terminals become weak low state (a state grounded through a high resistance). the protection mode can be cancelled by turning off the power supply or inputting an l level si gnal to sleepn terminal momentarily. and, when protn terminal is externally connected to sleepn terminal, automatic return mode is selected. at this time, the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and protn terminal output is turned from l level into hi-z state and a normal operation state is given after a given standby time (t wu ). (automatic return function) the current value to detect a short-circuiting between terminals is 8a (typ,v ddp =12v), 10a (typ,v ddp =15v). ~ high temperature protection function this is the function to protect the device by detecting an unusual te mperature in YDA148. the protection mode operates in the following two modes according to the temperature. 1) high temperature power limiter state if the temperature rises and reaches 155 c (typ.), the high temperature power limiter state is given. this state decreases the power limit level by 6db in order to limit th e digital amplifier output power, and attempts to lower the temperature. in this way, when the temperature falls and lowers than 130c (typ.), the high temperature power limiter state is automatically cancelled and the gain is restored to the original setting value. in the power limiter state, this does not affect on protn terminal. 2) high temperature cutoff state if the temperature rises and reaches 165 c (typ.) during the high temperature po wer limiter state, the high temperature cutoff state is given. this state outputs an l level signal from protn terminal and digital amplifier output terminals become weak low state (a state grou nded through a high resistance). in this way, when the temperature goes down and lowers than 130c (typ.), the high temperature cutoff mode is automatically cancelled. and, even if the cutoff state is established by detecting an unusual temperature, when protn terminal is externally connected to sleepn terminal, the cutoff state is cancelle d and protn terminal output is turned from l into hi-z state and a normal operation state is given if the temperat ure is sufficiently lowered after a given standby time (t wu ). (automatic return function) if the temperature is not sufficiently lowered, the hi gh temperature protection mode will be established. ~ low voltage malfunction prevention function this is the function to protect the device when the supp ly voltage at pvddreg termin al is unusually lowered. in this protection mode, the digital amplifier output terminals become weak low state (a state grounded through a high resistance). this protection mode is given if the supply voltage at pvddreg terminal becomes a voltage lower than pvdd shutdown threshold voltage (v huvll ). when the supply voltage at pvddreg termin al exceeds pvdd startup threshold voltage (v huvlh ), the protection mode is cancelled and a normal operation mode is given after a given standby time (t wu ). (automatic return function) free datasheet http:// YDA148 18 ~ dc detection function this is the function to protect the speaker connected to the digital amplifier output when a dc signal is continuously output from the digital amplifier. when muten terminal=l, the dc detection function is disabled. when a voltage in excess of a given time (t dcdet ) and a given level (v dcdet ) is output to the digital amplifier output, the dc detection mode is given. this state outputs an l level signal from protn terminal and digital amplifier output terminals become weak low state (a state grounded through a high resistance). once the dc detection mode is given, an l level signal keeps outputting from protn terminal even if the dc output state is cancelled. the protection mode is cancelled by turning off the power supply or inputting an l level signal to sleepn terminal momentarily. and, even if dc protection mode is established by detecti ng a dc signal, when protn term inal is externally connected to sleepn terminal, the protection mode is cancelled and protn terminal output is turned from l into hi-z state and a normal operation state is given after a given standby time (t wu ). free datasheet http:// YDA148 19 examples of application circuits (caution) ~ a ceramic capacitor of 1 f should be used as a bypass capacitor between the following terminals: pvddpl-pvssl, pvddml-pvssl, pvddpr-pvssr, and pvddmr-pvssr. please mount the cap acitor as close as possi ble to each terminal. ~ a former-stage impe dance of input terminals should be 10k ? or less. ~ select resistor values so that a voltage be comes 2.0v to 3.3v when protn terminal is at h level and current becomes 0.4ma or le ss when protn terminal is at l. ~ for plimit terminal sett ing, see page 5 and 6. ~ for a pull-up resistor for protn terminal, see pa ge 14 and 15. single operation in stereo mode (different ial-input, external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select v ssa free datasheet http:// YDA148 20 single operation in stereo mode (single-ended input, external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input+ rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select v ssa single operation in stereo mode (differential-input, input sign al level (externally set), external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select v ssa free datasheet http:// YDA148 21 single operation in stereo mode (single-ended input, input sig nal level (externally set), external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select v ssa single operation in monaural mode (differential-input, external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag non-clip/drc1/drc2 mode select external clock mute control sleep control 1uf 1uf 0.1uf lch input- lch input+ (open) v ddp 220uf ncdrc0 v ssa free datasheet http:// YDA148 22 single operation in stereo mode (differential-input, internal clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select avss v ssa single operation in stereo mode (differential-input, ex ternal clock operation, automatic return setting): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select external clock mute control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf ncdrc0 non-clip/drc1/drc2 mode select v ddp v ssp v ssa free datasheet http:// YDA148 23 master-slave operation (differential- input, external clock operation): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag non-clip/drc1/drc2 mode select external clock sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag non-clip/drc1/drc2 mode select sleep control 1uf 1uf 1uf 1uf 0.1uf lch input+ lch input- rch input+ rch input- master slave1 v ddp 220uf v ddp 220uf ncdrc0 mute control mute control ncdrc0 sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag non-clip/drc1/drc2 mode select sleep control 1uf 1uf 1uf 1uf 0.1uf lch input+ lch input- rch input+ rch input- slave2 v ddp 220uf mute control ncdrc0 (open) v ssa v ssa v ssa free datasheet http:// YDA148 24 master-slave operation (differentia l-input, external clock operati on, automatic return setting): sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select non-clip/drc1/drc2 mode select external clock 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select non-clip/drc1/drc2 mode select 1uf 1uf 1uf 1uf 0.1uf lch input+ lch input- rch input+ rch input- master slave1 v ddp 220uf v ddp 220uf ncdrc0 mute control mute control ncdrc0 sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select non-clip/drc1/drc2 mode select 1uf 1uf 1uf 1uf 0.1uf lch input+ lch input- rch input+ rch input- slave2 v ddp 220uf mute control ncdrc0 (open) v ssp v ddp v ssa v ssa v ssa free datasheet http:// YDA148 25 electrical characteristics ? absolute maximum ratings *1) parameter symbol min. max. unit power supply terminal (pvdd) voltage range v ddp -0.3 20 v input terminal voltage range v in -0.3 4 v protn terminal voltage range v protn -0.3 4 v power dissipation (ta=25 ? ) p d25 6.03 *2) w power dissipation (ta=70 ? ) p d70 3.86 *2) power dissipation (ta=85 ? ) p d85 3.14 *2) w junction temperature t jmax 150 c storage temperature t stg -40 150 c note) *1: absolute maximum ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability. *2: a value based on the following implementation conditions: lc filter l=22 [h]/c=0.47[h], board layer 4 layers(fr-4), board size 80 [mm] 60 [mm], board copper foil thickness 35 [m], wiring density 377%, device heat pad soldering on the board through hole for heat dissipation 9 (33) holes from a point just below the exposed stage to the inner layer (vss) and b layer. ? recommended operating condition parameter symbol min. typ. max. unit power supply voltage (pvdd) v ddp 8 - 16.5 v operating ambient temperature t a -40 25 85 c speaker impedance (stereo) r l 7.2 8 - ? speaker impedance (monaural) *3 r l 3.6 4 - ? note) *3: connect terminals between outpl and outpr and between outml and outmr before use. ? dc characteristics (v ss =0v, v ddp =8v to 16.5v, ta=-40 c to 85 c , ckin=1mhz, unless ot herwise specified. ) parameter symbol conditions min. typ. max. unit pvdd startup threshold voltage v huvlh - - 6.5 - v pvdd shutdown threshold voltage v huvll - - 6.0 - v dc detection voltage v dcdet pvdd=15v - 4 - v dc detection time t dcdet - - 0.5 - s digital terminal *4) h level input voltage v ih - 2.52 - - v digital terminal *4) l level input voltage v il - - - 0.9 v digital terminal *4 input impedance r in_d - 3.3 - - m ? sleepn terminal h level input voltage v ih_slpn - 2.0 - - v sleepn terminal l level input voltage v il_slpn - - - 0.8 v sleepn terminal input impedance r in_ slpn - 3.3 - - m ? ckout output voltage v ol i ol =4ma - - 0.4 v ckout output voltage v oh i oh =-4ma 2.4 - - v protn output voltage v ol i ol =0.4ma - - 0.4 v inlp, inlm, inrp, inrm terminals input impedance r in - - 18.8 - k ? avdd output voltage v dda 3.0 3.3 3.6 v avdd output current i dda - - 1 ma vref output voltage v ref - v dda /2 - v pvdd consumption current i ddp v ddp =12v, no-load - 32 - ma pvdd consumption current during power-down mode (sleepn=l) i sleep v ddp =12v, ta=25c - 20 - a pvdd consumption current during mute state (muten=l) i mute v ddp =12v, ta=25c - 16 - ma pvdd consumption current during no signal input i nosig v ddp =12v, ta=25c - 32 - ma note) *4: this value is applicable to muten, ckin, ncdrc0, ncdrc1, gain0 , and gain1 (cmos i/f) terminals. free datasheet http:// YDA148 26 ? ac characteristics (v ss =0v, v ddp =8v to 16.5v, ta=-40 c to 85 c , ckin=1mhz, unless otherwise specified.) parameter symbol min. typ. max. unit ckin input frequency f ckin 0.9 1.0 1.1 mhz ckin input duty dt ckext 40 - 60 % self-excited clock frequency f ck - 1.0 - mhz sleep recovery time t wu - 1 1.5 s mute recovery time t mrcv - - 1 ms ? analog characteristics (v ss =0v, v ddp =12v, ta=25 c , gain[1:0]=l,l, ncdrc[1:0]=l,l, ckin= ckin= l *6) , unless otherwise specified.) parameter symbol conditions min. typ. max. unit r l =8 ? , v ddp =12v, thd+n=10% 10 w maximum momentary output (stereo) po r l =8 ? , v ddp =15v, thd+n=10% 15 w r l =4 ? , v ddp =12v, thd+n=10% 19 w maximum momentary output (monaural) po r l =4 ? , v ddp =15v, thd+n=10% 30 w gain[1:0]=l,l 22 db gain[1:0]=l,h 28 db gain[1:0]=h,l 34 db voltage gain a v gain[1:0]=h,h 16 db total harmonic distortion rate (stereo) (bw::20khz) thd+n r l =8 ? ,p o =0.1w 0.01 % total harmonic distortion rate (monaural) (bw::20khz) thd+n r l =4 ? ,p o =0.2 w 0.16 % signal /noise ratio (stereo) (bw::20khz a-filter) snr r l =8 ? ,gain[1:0]=h,h 105 db signal /noise ratio monaural) (bw::20khz a-filter) snr r l =4 ? ,gain[1:0]=h,h 105 db residual noise (stereo) (bw::20khz a-filter) vn r l =8 ? ,gain[1:0]=h,h 48 vrms residual noise (monaural) (bw::20khz a-filter) vn r l =4 ? ,gain[1:0]=h,h 48 vrms channel separation ratio cs 1khz 80 db power supply rejection ratio (stereo) (pvdd applied) psrr vripple=100mv, f=1khz 60 db power supply rejection ratio (monaural) (pvdd applied) psrr vripple=100mv, f=1khz 60 db common mode rejection ratio (stereo) cmrr f=1khz 41 db common mode rejection ratio (monaural) cmrr f=1khz 41 db maximum efficiency (stereo) r l =8 ? 91 % r l =4 ? 93 % maximum efficiency (monaural) r l =8 ? 93 % output offset voltage (stereo) *5) |vo| 5 15 mv output offset voltage (monaural) *5) |vo| 5 15 mv f=20hz -1 0 1 db frequency characteristics f res f=20khz -1 0 1 db free datasheet http:// YDA148 27 note) *5: the offset voltage is denoted by considering a typical value and the maximum value as and 3 , respectively. *6: the same specification is applied to the external clock mode and internal clock (spread clock mode). all the values of analog characteristics were obtained in our ev aluation circumstance. depending upon pattern layout etc., characteristics may vary. the measurement is pe rformed with an 8 ? or 4 ? resistor connected in series with a 30h coil as an output load. free datasheet http:// YDA148 28 ? example of typical characteristics (v ss =0v, v ddp =12v, ta=25 c, gain[1:0]=l,l, ncdrc[1:0]=l,l, ckin=1mhz, unless otherwise specified) q free datasheet http:// YDA148 29 1 p x f s % j t t j q b u j p o w t 0 v u q v u 1 p x f s : % " t u f s f p 1 p x f s < 8 > 1 p x f s % j t t j q b u j p o < 8 > 7 ? 7 ? 7 ? 7 ? 1 p x f s % j t t j q b u j p o w t 0 v u q v u 1 p x f s : % " t u f s f p 0 v u q v u 1 p x f s < 8 > 1 p x f s % j t t j q b u j p o < 8 > 7 ? 7 ? 7 ? 7 ? 1 p x f s % j t t j q b u j p o w t 0 v u q v u 1 p x f s y : % " n p o p 0 v u q v u 1 p x f s < 8 > 1 p x f s % j t t j q b u j p o < 8 > 7 ? 7 ? 7 ? 7 ? 1 p x f s % j t t j q b u j p o w t 0 v u q v u 1 p x f s : % " n p o p 0 v u q v u 1 p x f s < 8 > 1 p x f s % j t t j q b u j p o < 8 > 7 ? 7 ? 7 ? 7 ? free datasheet http:// YDA148 30 package outline free datasheet http:// YDA148 31 free datasheet http:// YDA148 the specifications of this product are subject to improvement changes without prior notice. notice free datasheet http:// |
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